Microprocessors

Tue Jan 25, 2022 [Thu Apr 7, 2022]

Programmer’s Model x86 #

Scaled Index Addressing Mode only available in 32-bit processors i.e. 80386 and 80486.
Square brackets in ASM command indicates dereferencing of memory:
- mov [ebx], eax moves the value in eax to the memory address contained in ebx.
- mov ebx, [eax] moves the value from the memory address contained in eax to ebx.
Word Bit
- W=0: 8-bit data
- W=1: 16-bit data
All Intel processors use little endian representation, i.e. lower byte first and then higher byte.
In 1985 Intel introduced 80386, the first 32-bit processor in the x86 line.
- The main registers were extended to 32 bits by adding an E prefix
- EAX stood for extended AX. And AX now refers to the lower half of EAX, while AH and AL continue to refer to the two AX bytes.
One can copy data to DS only from AX register. i.e. only MOV DS, AX works for DS.

Absolute Addressing: all address lines from \(A_0 - A_{19}\) are used
- Preferred because later we might expand memory
Incremental Addressing: Only the required address lines are used

To complete memory read or write in one clock cycle, the memory is set up as two banks: odd and even banks, each of size 512K.
Lower order data bus \(D_0 - D_7\) is connected to even address bank and higher order to odd address bank.
\(A_0\) is used for enabling the even memory and \(BHE’\) for enabling the odd memory.
Word transfer starting at an odd address takes two bus cycles
- When a word is read from an odd address, one byte is in one word, the other byte in another.
- You cannot address both bytes at the same time. If the 8086 wants to read a word at addresses 125-126, it can’t get it this way, because those two addresses have different bits on A19:A1.

INT instruction
Internal interrupt, exception in program execution
Trap, single-step mode of operation: interrupt after every instruction
- Trace Flag (TF) should be enabled
- Used to check if program is running properly

INT 0: Divide by Zero, quotient is too large
INT 1: Single step interrupt, will be executed after every instruction if trap flag is set
INT 2: NMI, rising edge triggered, cannot be disabled
INT 3: Breakpoint routines, used for debugging
INT 4/INTO: If overflow after arithmetic operation, interrupt invoked else nop
INT 5:
INT 6: Invalid opcode
INT 8: double fault, two errors at once e.g. div
INT 9: in real mode, data/code segment shouldn’t exceed 64K
INT B: Segment not present, P=0

Most I/O devices will be 8-bit (only \(D_0-D_7\)
Unlike in memory interfacing, either only even or only odd bank is used in I/O interfacing
- This reduces theoretical 256 device connections to 128
32-bit processors: 64 input devices can be connected (Only every 4th address can be used)
Simplest input device: Switch
Simplest output device: LED
We need buffers for input devices and latches for output devices
- So we connect the i/o devices to a port which connects them to the processor
  - Ports are also known as interfacing devices/interfacing controllers/peripheral devices
  - e.g. 8255
Polling: keeps checking if data available, waste
- Interrupt is preferred to know if data available
- CS: Chip select

Programmable interrupt controller (PIC)
PICs typically have a common set of registers: interrupt request register (IRR), in-service register (ISR), and interrupt mask register (IMR). The IRR specifies which interrupts are pending acknowledgement, and is typically a symbolic register which can not be directly accessed. The ISR register specifies which interrupts have been acknowledged, but are still waiting for an end of interrupt (EOI). The IMR specifies which interrupts are to be ignored and not acknowledged. A simple register schema such as this allows up to two distinct interrupt requests to be outstanding at one time, one waiting for acknowledgement, and one waiting for EOI.